1. Technical Field
The present invention relates to a method of forming semiconductor devices, and more particularly, to a method of forming a dual damascene metal interconnection employing a sacrificial metal oxide layer.
2. Discussion of the Related Art
With the increase of integration degrees of semiconductor devices, the process of metal interconnection fabrication is becoming increasingly important in affecting reliability of semiconductor devices. Metal interconnections are associated with problems such as RC delay, EM (electro-migration), or the like. As one of the methods of solving the problems, a copper interconnection and a low-k dielectric layer are employed on a semiconductor device, and a damascene process is used to form a copper interconnection.
A dual damascene process comprises forming a via hole exposing a lower interconnection, and a trench intersecting the upper portion of the via hole, filling the via hole and the trench with a metal material such as copper, and forming a metal interconnection and a via plug at the same time, through a chemical mechanical polishing (CMP) process. The dual damascene metal interconnection means a metal interconnection formed by the dual damascene process.
Further, a dual damascene process of first forming a via hole, and then forming a trench may be referred to as a via first dual damascene (VFDD) process. However, the VFDD process may provide a lack of process margins of a photolithography process, in comparison with a typical photolithography process of forming a via hole or a trench only. Particularly, as a problem, there may be considered a process margin of a photolithography process of forming the trench after forming the via hole. Further, etch damage may be caused_in the lower interconnection exposed through the via hole during the formation of the trench.
A method of preventing etch damage of the lower interconnection and increasing a process margin of a photolithography process is described in U.S. Pat. No. 6,329,118, entitled, “Method for patterning dual damascene interconnects using a sacrificial light absorbing material,” to Hussein et. al.
In the method disclosed in U.S. Pat. No. 6,329,118, a via hole, formed inside an insulating layer, is filled with a sacrificial light absorbing material, and a photoresist pattern is formed on the sacrificial light absorbing material to form a trench. Then, using the photoresist pattern as an etch mask, the sacrificial light absorbing material and the insulating layer are etched to form the trench.
The sacrificial light absorbing material reduces substrate reflectivity during an exposure step in a photolithography process, and improves a capability of controlling a critical dimension (CD) and a CD uniformity. Further, the sacrificial light absorbing material may be dry etched at substantially the same rate that the insulating layer may be dry etched, and wet etched at a significantly faster rate than the insulating layer may be wet etched. Therefore, lower interconnects exposed through the via hole can be protected during the formation of the trench.
However, as the integration of semiconductor devices further increases, a pitch of the trench is further reduced. In the case that a design rule is 90 nm or less, it is difficult to form a photoresist pattern having an appropriate pitch just with an exposure step using a KrF laser. Furthermore, in order to etch an insulating layer using the photoresist pattern as an etch mask, a photoresist layer is required to have a thickness above a predetermined level. Thus, a photolithography process using a KrF laser as above is led to a lack of process margins such as a resolution and a depth of focus (DOF). To comply with this, there is employed a photolithography process using an ArF laser. The photolithography process using an ArF laser is advantageous in improving resolution, and allowing the formation of a much finer photoresist pattern in comparison with the conventional photolithography process using a KrF laser. However, the photoresist layer for ArF has a lower etch resistance than the photoresist layer for KrF. As a result, an etch process of forming a trench using the photoresist pattern as an etch mask cannot provide desired process margins.
Therefore, the dual damascene process of forming a trench using the photoresist pattern as an etch mask by the method disclosed in U.S. Pat. No. 6,329,118 cannot ensure process margins of photolithography and etch processes at the same time, in the recent trends of highly-integrated semiconductor devices.